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Altera_Forum's avatar
Altera_Forum
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16 years ago

Timing Constraints for Startix II

Hello,

up to now i used to work with small frequencies and I only set the fmax parameter appropriately. In my current project i have some data paths with 275MHz clock and i wanted to constrain the registers on the data path (pipelined) with appropriate setup and hold times (Im using Classic Timing Analyzer). Could comeone please explain me where to start ? Where can I acquire these parameters from ? Are the registers internal Tsu and Th already somehow constrained and I should not worry about them ?

On the other hand, I found in the Startix II handbook following sentence "Violating the setup or hold time on the memory block address registers could corrupt memory contents." Logically, I understand that i must set them appropriately, but dont know where to take the values from...

Best regards

Joel

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Normally, for all internal registers(except first input registers and last output register) quartus takes responsibilty not to violate timing. Each launch edge to each latch edge relation is known to quartus and the fitter inserts delays as appropriate to meet the requirements of register timings, provided ofcourse it knows the clk speed at each register. The user is responsible at io registers.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Yeah, as i thought, but I wasn't sure. Anyway, this approach is most logical. Thank you for making it clear.

    PS. I also need to group a number of ouput pins and set a hold time value for them. Could someone please tell me how to do it within a TCL script ?

    Best regards

    Joel