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Altera_Forum
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15 years ago

Timing constraints dont appear to work on Strobed outputs

Hello, I have the following SDC constraints defined, which are just a test to constrain three signals from my FPGA feeding a TI DSP : Output signals from FPGA to DSP: had[1], had[0], hrnw ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi Kaz,

Yes thanks for the response....and i get your drift ! You have to be careful to extracty the rigt timing values form the datasheet , and know how to apply them correctly in SDC format. Its very easy to misinterpret this data and get it wrong, so the FPGA passes tming analysis but because the constraints dont match reality, it still fails in the ral world.

cheers :)