Altera_Forum
Honored Contributor
14 years agoTiming constraints dont appear to work on Strobed outputs
Hello,
I have the following SDC constraints defined, which are just a test to constrain three signals from my FPGA feeding a TI DSP : Output signals from FPGA to DSP: had[1], had[0], hrnw # create setup hold board delays from TI DSP datasheet: # DSP Setup & Hold timing HAS Strobe low before HCNTL[1:0] and hrnw set HAS_Setup 5 set HAS_Hold 3# set max and min est DSP to FPGA delays set Max_fpga2dsp 2 set Min_fpga2dsp 1 set HASOutputDelayMax [expr $HAS_Setup + $Max_fpga2dsp] set HASOutputDelayMin [expr $HAS_Hold + $Min_fpga2dsp] # Setup clocks # Set period for EHPI base clock set ehpi_base_period 25.201# create constraint for input clock pin to PLL create_clock -name inclk0 -period $ehpi_base_period [get_ports inclk0] derive_pll_clocks set_clock_groups -asynchronous -group {inclk0 EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] }# Create Generated Clock for STROBE write output HAS# create_generated_clock -name HAS_STROBE -source EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] [get_ports has_n] create_generated_clock -name HAS_STROBE -source [get_pins {EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_registers {bidir_interface:uut|has_n}] derive_clock_uncertainty # Setup output constraints on three output signals: had[1], had[0], hrnw # *************************************************************************************************************# Constrain EHPI to DSP CTRL strobed output paths# *************************************************************************************************************# Output MAX delay on HAS bus : using EHPI Virtual Address strobe set_output_delay -clock HAS_STROBE -max $HASOutputDelayMax [get_ports {had[0] had[1] hrnw}]# Output MIN delay on HAD bus : using EHPI Virtual Address strobe set_output_delay -clock HAS_STROBE -min $HASOutputDelayMin [get_ports {had[0] had[1] hrnw}] I compiled the design...run TimeQuest....and get the following report after generation of all reports : report_timing -setup -npaths 100 -detail full_path -to_clock HAS_STROBE -panel_name "HAS_STROBE||setup" Info: Report Timing: No setup paths were found Info: -to_clock [get_clocks {HAD_STROBE}] Info: -setup Info: -npaths 100 Info: -detail full_path Info: -panel_name {setup} 0 0.000 I was expecting to see three setup paths here ....anybody know what is wrong ? Also, how would i tell TimeQuest that the Strobe clock usues a negative edge ? Many thanks for your help ! :)