Timing constraints dont appear to work on Strobed outputs

As far as I know, Timequest checks the tSU/tH on any path between two internal fpga registers.

Though an external device input registers or external device output registers are part of the same RTL chain from designer perspective but timequest does not report on these external paths as violations but rather as tSU/tH on fpga input registers or tCO on its output registers and it is left up to you to check if it is ok.

Thus many designs may seem passed timing falsley if you enter wrong external requirement figures. This is very common...

The same applies to recovery/removal and unless reset is generated internaly then timequest has no idea about when it changes. Though I think there is a way to inform it using max/min input delay on reset pin.