Timing Constraint problem on set_input_delay for Video LVDS Rx

I want to capture the LVDS_A_CK with the clock INT_IOCLKA generated by PLL following the timing in the visio.So I do the timing constraints as follows.

set_max_delay -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} [expr 1.099 + 2.197]

set_min_delay -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} [expr 1.099 - 2.197]

2.197 is the half of Cycle of INT_IOCLKA,and 1.099 is the shift phase value of INT_IOCLKA.

Are the timing constraints right?