timing constraint for output mux and how to set output delay.

Thanks for your information.

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After the on-line training, i have learned some skill for setting constraint source synchronous system.

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But i still have a question.

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The train class shows the FPGA ports are only one use.( clock port is clock, data port is data)

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In my design, i have two different source synchronous signals will use the same ports.

FPGA port will be clock pin or data pin for different interface. ​

ex : port A is not only the data1 of interface1, but also the clock of interface2.

portD is not only the clock of interface 1, but also the data3 of interface2.

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How to set two different desired constraint on the same FPGA port?

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Thank you.

Andy

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