Forum Discussion
ATsao3
New Contributor
New Contributortiming constraint for output mux and how to set output delay.
Hi, I’m looking for some help to constraint my design. I didn’t write constraint before and i look some documents on internet. Still can’t find any example similar to my design. My design has two i...
ATsao3New Contributor
New ContributorThanks for your information.
After the on-line training, i have learned some skill for setting constraint source synchronous system.
But i still have a question.
The train class shows the FPGA ports are only one use.( clock port is clock, data port is data)
In my design, i have two different source synchronous signals will use the same ports.
FPGA port will be clock pin or data pin for different interface.
ex : port A is not only the data1 of interface1, but also the clock of interface2.
portD is not only the clock of interface 1, but also the data3 of interface2.
How to set two different desired constraint on the same FPGA port?
Thank you.
Andy
