timing constraint for output mux and how to set output delay.

You're essentially creating a source synchronous single data rate (SDR) output interface. There's quite a few constraints involved, so check out this training first:

https://www.intel.com/content/www/us/en/programmable/support/training/course/ocss1000.html

You'll need a generated output clock constraint, output delay constraints, a false path constraint for the clock, and potentially a multicycle exception. Post again if you want a check of your code after seeing the training.

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