Forum Discussion
MKlee2
New Contributor
New ContributorTiming constrains between 2 independent clocks with same frequency
Hi,
I’m trying to connect user logic to a stratix10 H-Tile phy. For the rx and tx path I have user logic connected to the phy, driven by the tx/rx clocks provided by the phy itself. Now I want to...
Macnica_FAENew Contributor
New ContributorIf you have a set_clock_groups asynchronous command, then the tool won't check that clock crossing. And as you can see, the violations are indeed for a clock crossing, since #1 they are being checked and #2 they show up as launch clock and latch clock. What are you doing for the "handshake"? That should be a fifo of some sort then, and it will include (internal, invisible perhaps) a false path so that timing is not checked.
