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Altera_Forum's avatar
Altera_Forum
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12 years ago

timing constrain of adc and fpga interface with data,fco,dco signals.

hi.

In my design, there is a ADC chip adc9228. The ad9228 output serial data D+/D- with data clock DCO+/DCO- and frame clock FCO+/FCO-. DCO latches data at both edges.FCO's rising edge indicates the first bit of adc data. How to constrain timings with timequest?

https://www.alteraforum.com/forum/attachment.php?attachmentid=7502

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I would just create a clock with the entire period, quartus will now to do timing analysis on the falling edge by analyzing your rtl code.