Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

timing constrain of adc and fpga interface with data,fco,dco signals.

hi. In my design, there is a ADC chip adc9228. The ad9228 output serial data D+/D- with data clock DCO+/DCO- and frame clock FCO+/FCO-. DCO latches data at both edges.FCO's rising edge indicates t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I would just create a clock with the entire period, quartus will now to do timing analysis on the falling edge by analyzing your rtl code.