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Honored Contributor
Honored ContributorTiming Analyzer not deriving PLL clock
Hi Folks, I am using a Cyclone III EP3C10. In my design I have an altlvds_rx module being fed from a 40MHz clock. I also have an altpll generating three clocks from a 50MHz base clock. The LV...
Altera_ForumHonored Contributor
Honored ContributorHi, found my problem. the 200MHz altpll clock was not feeding any logic and so was optimized out. oops
D
