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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Timing analysis error on Asynchronous control signals

Hello, In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

You're coding them like clocks so the tool will think they're clocks.

What do your false path constraints look like?

  • NShan12's avatar
    NShan12
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    The false path constraints are as follows:

    set_false_path -from [get_ports WRN]

    set_false_path -from [get_ports ALE]