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Altera_Forum's avatar
Altera_Forum
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16 years ago

timescale related query ..

Can anyone explain why the simulator shows the following output for the below verilog code : Output : run # 0x Thanks a ton in advance! -----------------------...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Well you are asking me to dig pretty deep into memory but I believe the "run" command alone will run a single timestep. In your case that is 10ns.

If you want to run the simulator to the end of the simulation you issue a "run all" command. However, you must define what the "end" of the simulation is. Typically the end is indicated by either a "$finish" or "$stop" directive in your testbench. If you don't have something to stop the simulation in the testbench, it will run indefinitely.

Jake