timescale related query ..

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Can anyone explain why the simulator shows the following output for the below verilog code :

Output :

run

# 0x

Thanks a ton in advance!

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`timescale 10ns/ 1ns

module toy ( a, sel, y );

input a,sel;

output y;

reg y;

initial

$monitor ( $time, y );

initial

begin

#0 y = 1'b0;

#20 y = 1'b1;# 11.1 y = 1'b0 ;

end

endmodule

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Hi,

the signal y is not defined from 0 until 20ns. Thats why you got the 0x.

Kind regards

GPK