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Altera_Forum's avatar
Altera_Forum
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11 years ago

TimeQuest User Guide Question

I have a question regarding the virtual clock assignment described in the TimeQuest User's Guide on the web. I am not sure I understand how the virtual clock created for the set_input_delay and set_output delay constraints is related to the actual clock driving the logic in the FPGA.

I have the following constraint for CLK_FPGA which clocks all logic in the device:

create_clock -name { CLK_FPGA } -period 13.333 { CLK_FPGA }

Then, according to the paper, I create a virtual clock for I/O timing:

create_clock -name { CLK_VIRTUAL } -period 13.333

Then I set the I/O constraints (whose logic used CLK_FPGA) and relate them to CLK_VIRTUAL:

set_input_delay -max 5.000 -clock { CLK_VIRTUAL } [get_ports { LAD }]

set_input_delay -min 1.000 -clock { CLK_VIRTUAL } [get_ports { LAD }]

set_output_delay -max 8.000 -clock { CLK_VIRTUAL } [get_ports { DOUT }]

set_output_delay -min 2.000 -clock { CLK_VIRTUAL } [get_ports { DOUT }]

How is CLK_VIRTUAL associated with CLK_FPGA? They only have identical periods in the create_clock constraints, does that make them related?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Let me take the set_input_delay case.

    In principle if you know the data offset from clock edge at fpga you just enter that directly relative to your fpga clock. As such if you use virtual clock it will do nothing whatsoever.

    The idea of virtual clock is to represent the clock source of external input register and is only useful if you:

    1) don't know the offset direct at fpga but

    2) you know the tCO of external device and board delay

    if you know the board delay then you might think that offset = tCO + board delay.

    3)However if clock to external device register is delayed such as through a buffer (relative to fpga clock pin) then you need to add that delay to virtual clock.

    In other words the virtual clock - though does not exist in fpga - but is meant to complete the rtl chain.