TimeQuest User Guide Question

Let me take the set_input_delay case.

In principle if you know the data offset from clock edge at fpga you just enter that directly relative to your fpga clock. As such if you use virtual clock it will do nothing whatsoever.

The idea of virtual clock is to represent the clock source of external input register and is only useful if you:

1) don't know the offset direct at fpga but

2) you know the tCO of external device and board delay

if you know the board delay then you might think that offset = tCO + board delay.

3)However if clock to external device register is delayed such as through a buffer (relative to fpga clock pin) then you need to add that delay to virtual clock.

In other words the virtual clock - though does not exist in fpga - but is meant to complete the rtl chain.