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Altera_Forum
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16 years ago

TimeQuest .sdc constraints for EPCS (ALTASMI_PARALLEL megafunction)

Hi all, I'm using the ALTASMI_PARALLEL megafunction to access a EPCS16 device at 25MHz (active serial) on a Cyclone III device. The EPCS16 is 2 centimeters away from the FPGA (very small PCB ...
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Altera_Forum
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14 years ago

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I think I've actually hit a bug related to hold timing violation of data output from the hard ASMI block to the first flip-flop in the shift register in ALTASMI_PARALLEL. The tool doesn't appear to time that path. On some builds (~1 out 20) the timing is precisely off such that there is a hold violation on that path, and I get inconsistent data on the ALTASMI_PARALLEL dataout port from one read to another. Probing internally on the FPGA with signal probe, I see that data is correct coming out of ASMI but incorrect after it is latched into the shift-register.

So much for not having timing constraints :( Opening an SR with Altera.

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Hi,

thanks for posting this here. Can you let us know what the answer from Altera was?

Thanks!