TimeQuest .sdc constraints for EPCS (ALTASMI_PARALLEL megafunction)

I think I've actually hit a bug related to hold timing violation of data output from the hard ASMI block to the first flip-flop in the shift register in ALTASMI_PARALLEL. The tool doesn't appear to time that path. On some builds (~1 out 20) the timing is precisely off such that there is a hold violation on that path, and I get inconsistent data on the ALTASMI_PARALLEL dataout port from one read to another. Probing internally on the FPGA with signal probe, I see that data is correct coming out of ASMI but incorrect after it is latched into the shift-register.