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Altera_Forum
Honored Contributor
16 years agoTimeQuest .sdc constraints for EPCS (ALTASMI_PARALLEL megafunction)
Hi all, I'm using the ALTASMI_PARALLEL megafunction to access a EPCS16 device at 25MHz (active serial) on a Cyclone III device. The EPCS16 is 2 centimeters away from the FPGA (very small PCB ...
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- For this altasmi_parallel core and the dedicated AS pins, you don't need to add any timing constraint on it, and you don't need to do timing analysis. --- Quote End --- Hi, I've noticed that the post is a bit old, but... on what do you base your statement? Have you found this recommendation anywhere? Typicall when Altera generates some core (e.g. Nios) it will also generate a corresponding .sdc file. For ASMI I haven't seen any, so I just thought I have to constrain it, just in case...