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Altera_Forum's avatar
Altera_Forum
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14 years ago

TimeQuest red fail path VS simulation success

when I compile,the "timequest timing analisis" shows that "setup summary" has some red warning,i.e.my project has some failed path. But when I run the gate level simulation in slow model,the whole...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Also, find the failing path, look at the source change in the simulation and see if the latch register is catching it a cycle late, as it should. You should then look into why the testbench doesn't fail. This might help verify why TimeQuest caught something that a timing simulation did not.