TimeQuest red fail path VS simulation success

Timing simulations often don't catch timing issues. That's part of the reason lots of people don't use them anymore. TimeQuest checks a range of requirements, across multiple timing models. For example, a 10ns clock will have a hold of 0ns and setup of 10ns, making sure the transfers occur within that range.

The only time simulations show a true timing error is if the micro setup or micro hold is violated. For example, if the latch edge hits the register at time 10ns, the data can't change a small time before or after that, say something like 50ps. That's the micro-setup or micro-hold of the register. But let's say in the slow model the data changes 200ps after the edge. The simulator won't explicitly say anything is wrong. If your test bench signals a problem because of that, you can trace it back, but it's pretty easy to miss something.

As an example, let's say you had an 8-bit word of data sent from one set of 8 registers to the next set, and it's a 10ns requirement. But let's say it fails timing and takes 12ns to get to the next set of the registers. In a timing simulation, they would all get there a cycle later, and your testbench might have no idea it's a cycle late, as the data is still "good". But in hardware, as it varied over temperature, they might run a little faster, where some of the data bits travel faster than 10ns and some longer. Now your word of good data is being mixed across two cycles and it fails. The testbench would never catch that though.