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Altera_Forum's avatar
Altera_Forum
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7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Yeah, some time ago I had tried to instantiate a dual-clock FIFO IP because I was sick and tired of false-path'ing and using synchronizers each of my timing-irrelevant paths, but the IP wizard's GUI failed - probably because I'm running Quartus on a non-supported Linux distro.

So your idea does have merit and I think I'll revisit that again, especially if it'll allow the fitter to make the less than 416.66ps window needed for non-metastability across all phases when clocked at 300MHz.

Thanks,

-E