Timequest constraints for a dynamically phase-shifted PLL

As for solutions, is there a way in which you could utilize a dual clock fifo? By nature, you would cut paths between the 2 clocks therefore, phase of the 300 MHz clock doesn't really matter, only frequency (which doesn't change regardless of phase setting).

So I'm thinking that you could clock data into the fifo on each edge of the 50MHz clock and clock it out of the fifo when it indicates NOT empty. The data coming out would naturally be synchronized to the phase shifted clock. Again, I'm not quite sure what you are trying to achieve overall but it seems that this approach might deserve some consideration.