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Altera_Forum
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7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Ah, okay - I already have such data-gating in my actual code for when the latched clock is in the process of being shifted. The problem of concern is why there's apparent metastability long after the shifting has taken place i.e. effectively once 'clock_enable' is set.