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Altera_Forum
Honored Contributor
Honored ContributorTimequest constraints for a dynamically phase-shifted PLL
I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_ForumHonored Contributor
Honored ContributorA clock enable is usually written like this:
always_ff @(posedge dynshift_clk) begin if (clock_enable == 1'b1) begin d <= c[11]; end end But, I cannot say if using a clock enable actually helps in your application.
