Timequest constraints for a dynamically phase-shifted PLL

Clock enables are not the same as gated clocks though (the clock would still be running freely but the clock enable would enable the register). There may be some of your clock phases where the latch register is sampling the data input in a time frame where the result could be metastable or uncertain (I think that much is clear from the description of your problem). So simply relaxing the setup time with a multicycle constraint does not alter the outcome.

Imagine a system where you generate a series of clock enable signals which enable the latch register clocked by the selected 300 MHz clock phase; now in that system, the multicycle constraints would make sense because they describe exactly when the actual launch and latch occur. You only have half of the solution and that is the constraints. This is how I see it anyway. I'm not suggesting that the clock enable idea is a solution because I don't fully understand what the firmware is attempting to achieve and I can only see the small bit currently under the microscope.