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Altera_Forum
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8 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

With respect, I'm not sure if you understood what I am asking (you say that you "believe you did"??). It is all very well to apply your constraints as you have (and the images show the relaxed setup relationships etc), but the fact is that without specific clock enable signals to enable the latch register at the appropriate time, you are setting things up for timing failure or metastability.