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Altera_Forum
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7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

So are you generating appropriate clock enables to sample the signal with enough setup and hold time for each clock transfer at each phase setting? It's not enough just to define a multicycle constraint as that will not alter the physical clock relationship and if this is the case then I would expect metastability issues to arise.