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Altera_Forum
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7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Yeah, it fails timing without the relaxed constraints, because there's a default setup relationship of 416.66 picoseconds for the 45-degree phase shift (because the phase shifted clock is running 300MHz therefore a 3.333 nanosecond period, and then the divide by eight for the phase shifts).