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A variable phase-shifted clock domain has to be considered as asynchronous to other clocks, respective synchronization methods for domain crossing data signals are required. Timing constraints don't help because STA isn't able to check a variable timing.
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Is it?
Lets say that we have clock CLK_A which feeds PLL with one output, PLL dynamic phase shift feature is used and PLL can generate two clocks CLK_B_0deg or CLK_B_90deg on same output. Data is launched from CLK_A domain and latched in CLK_B_0deg/CLK_B_0deg domain.
so we have following constrains:
#Base clock
create_clock -period 10 -name CLK_A
# PLL constrains
create_generated_clock -name CLK_B_0deg
-master
-source ]
-phase 0 ]
create_generated_clock -name CLK_B_90deg
-master
-source ]]
-phase 90 ]
-add
# Clock groups
set_clock_groups -exclusive -group {CLK_B_0deg}
-group {CLK_B_90deg} \
CLK_B_0deg and CLK_B_90deg can not be active both in same time, any paths between those two clocks are cut. So TimeQuest should detect that CLK_A is synchronous to CLK_B_0deg and CLK_A is synchronous to CLK_B_90deg. If my understanding is correct we should be able to generate following timing reports:
1 - from CLK_A to CLK_B_0deg.
2 - from CLK_A to CLK_B_90deg.
And we should be able to see if one of those paths fail timing and one of those PLL clock phases can not be used right?
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