Timequest constraints for a dynamically phase-shifted PLL

eh291, what clock transfers does Timequest report? Presumably it does not report any between the multiple phases but at the boundary of the logic, are there any transfers between some other clock and each of the phases? Are these analyzed separately and do they all meet timing?

FvM, shouldn't Quartus report a critical warning if it cannot analyze this type of timing arrangement? There are examples in the cookbook of multiple clocks on a single node and I don't see how this is any different.