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Altera_Forum's avatar
Altera_Forum
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7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

A variable phase-shifted clock domain has to be considered as asynchronous to other clocks, respective synchronization methods for domain crossing data signals are required. Timing constraints don't help because STA isn't able to check a variable timing. I guess that Timequest is simply calculating timing for the initial phase shift of the respective clock output.

By the way, 99% of random results in case of timing violations are not caused by true metastability but simple clock and data delay variations if a is latched in more than register.