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Altera_Forum
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7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi vlrean,

Items 1 thru 6 you list are already done - my timing is fully constrained, and there are no errors reported.

] As I understand you have some timing related issues when running on hardware but TimeQuest reports say that there are no timing errors in all corners?

Correct.

] Maybe you have added some false path exceptions where you should not?

Yeah, that was one of the first things I thought of, but the affected path has the correct timing relationship, as verified by Timequest's reports.