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Altera_Forum
Honored Contributor
Honored ContributorTimequest constraints for a dynamically phase-shifted PLL
I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_ForumHonored Contributor
Honored ContributorIt's not clear what you mean by "activating one cycle early or late". However could it be that you are expecting a given phase to be "later" than another particular phase i.e. lag rather than "early" or lead?
I mean once it has activated, does it work fine? Does it malfunction in any other way? Is it just that the time of so called "activation" is not what you expect?
