TimeQuest + PLL Switchover + SDRAM

I am doing a design on Cyclone III. I have two clock inputs clk and hiclk. Both are of the same frequency and only one is active at a time (the other is used as a backup clock source). Inside FPGA, I use a PLL to connect to these two clocks (using auto-switch configuration) and multiply the frequency by 2. My sdc for this looks like:

create_clock -name {hiclk} -period 50.000 -waveform { 0.000 25.000 } [get_ports {hiclk}]

create_clock -name {clk} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk}]

set_clock_groups -exclusive -group {clk} -group {hiclk}

create_generated_clock -name {hiclk_system} -source [get_pins {inst2|altpll_component|auto_generated|pll1|inclk[1]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {hiclk} [get_pins {inst2|altpll_component|auto_generated|pll1|clk[0]}] -add

create_generated_clock -name {clk_system} -source [get_pins {inst2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {clk} [get_pins {inst2|altpll_component|auto_generated|pll1|clk[0]}] -add

create_generated_clock -name {hiclk_sdram} -source [get_pins {inst2|altpll_component|auto_generated|pll1|inclk[1]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {hiclk} [get_pins {inst2|altpll_component|auto_generated|pll1|clk[1]}] -add

create_generated_clock -name {clk_sdram} -source [get_pins {inst2|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {clk} [get_pins {inst2|altpll_component|auto_generated|pll1|clk[1]}] -add

I've made an SOPC Builder design with an SDRAM. One of the outputs of the PLL goes to an output pin to clock the SDRAM. As per the SOPC Builder User Guide I'm trying to setup the SDRAM I/O timing relative to that clock. The sdc looks like this:

create_generated_clock -source [get_pins {inst2|altpll_component|auto_generated|pll1|clk[1]}] -offset 0.5 [get_ports {sd_clk}]

set_input_delay -clock sd_clk -max [expr 5.4 + 0.6] [get_ports {sd_data*}]

set_input_delay -clock sd_clk -min [expr 3.0 + 0.4] [get_ports {sd_data*}]

set_output_delay -clock sd_clk -max [expr 2.0 + 0.6] [get_ports {sd_a* sd_b* sd_cas sd_cke sd_cs sd_d* sd_ras sd_we}]

set_output_delay -clock sd_clk -min [expr -1 + 0.4] [get_ports {sd_a* sd_b* sd_cas sd_cke sd_cs sd_d* sd_ras sd_we}]

The problem is that when I run TimeQuest there is a warning is generated saying the master clock could not be derived and that sd_clk was not created. If I click on it for more info I find that TimeQuest understands that hiclk_sdram and clk_sdram are both potential master clock candidates. If I force a master clock with something like:

create_generated_clock -source [get_pins {inst2|altpll_component|auto_generated|pll1|clk[1]}] -offset 0.5 -master_clock {clk_sdram} [get_ports {sd_clk}]

Then TimeQuest is happy but I am unsure if I have properly constrained the SDRAM I/O.

What is the right way to properly constrain the SDRAM I/O in this situation.