Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
That is irrelavent. HDLs runs in zero time, so in theory everything updates immediatly.
To get the FMax on a real FPGA, you need to compile the design and run timequest. - Altera_Forum
Honored Contributor
Thank you for your reply. But I have a clocked process which does not update variables immediatly. Please have a look at my previous post:
http://www.alteraforum.com/forum/showthread.php?t=37639 - Altera_Forum
Honored Contributor
--- Quote Start --- But I have a clocked process which does not update variables immediatly. Please have a look at my previous post. --- Quote End --- The previous post brings nothing but guesses. No problem is substantiated. I assume, it's just a simulation problem. Or the real code hasn't been posted.