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Altera_Forum
Honored Contributor
13 years agoThat is irrelavent. HDLs runs in zero time, so in theory everything updates immediatly.
To get the FMax on a real FPGA, you need to compile the design and run timequest.That is irrelavent. HDLs runs in zero time, so in theory everything updates immediatly.
To get the FMax on a real FPGA, you need to compile the design and run timequest.