Time delay in VHDL

Maha,

Both replies before mine are correct. I suspect you might need a little bit more to fully understand what is going on.

You will need to use a clock in your design. You will need to decide what the speed of that clock is going to be (this is the frequency of an oscillator out side of the FPGA that might be in a test board as an example). You can take that clock into the FPGA (as a signal called clk if you like) and use that to feed a counter.

For every count of the counter, you will then havea certain amount of "time" that will be consumed.

From there, you can take your input signal, and gate it with the result of the counter reaching a certain value, then allowing the signal to pass (basically and AND function when the counter reaches a desired length).

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If the time delay is not very large (compared to the frequency of the clock, then you simply use a series of Registers and pass along the signal for the input to out for the number of registers * 1/f of the clock. Result is a Delay of the signal as it clocks through the registers to the final output (this is basically a shift register).

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It really all depends on the amount of delay and the speed of the clock as to which is the best way to do it. (Best here meaning how much internal resources you can afford to use in the FPGA to accomplish the desired result).

Good lunk in your studies.

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