Altera_Forum
Honored Contributor
Honored ContributorTime delay in VHDL
I need to implement a time delay element in FPGA by VHDL language to delay a signal for a specified time. Please, any one here can help me. thanks very much.
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributoryou will need a counter, and then use that to wait until the specified time.
delays, like a <= b after 10 ns; are not synthesisable. The delay part is ignored.
