Honored ContributorI have a signal, that is input to EPM1270T144CN. That is not a periodic signal. There are only two pulses. I want to delay them by 25 nsec at the output. Is there a way to do this, as per required time delay in quartus 2?
Honored ContributorRaw delay but just going through signals is really hard to do and has really poor accuracy over PVT. My rough rule of thumb is that something can vary by 50%, i.e. if you delayed it by 33.33ns at the slow corner, it could be as fast as 16.66ns in the fast corner, so +/-8.33ns from your requirement. (I don't know why I'm using decimal points, as that's a really rough rule of thumb).
Honored ContributorHi Rysc
If you do not mind, can you explain me how to do it ? I am very new to CPLD and FPGAs.Honored ContributorHonored ContributorFrom pin-to-pin, probably the quickest way is to do:
set_max_delay -from [get_pins {din_a din_b}] -to [get_pins {delayed_a delayed_b}] 25.0 set_min_delay -from [get_pins {din_a din_b}] -to [get_pins {delayed_a delayed_b}] 25.0 Now, that's saying it has to be a perfect 25ns, which is impossible to dial in that precise and impossible over PVT, so to actually meet timing you need to expand them: set_max_delay -from [get_pins {din_a din_b}] -to [get_pins {delayed_a delayed_b}] 33.33 set_min_delay -from [get_pins {din_a din_b}] -to [get_pins {delayed_a delayed_b}] 16.66 This relies on the router adding delay to meet your minimum requirement, and to be honest, I'm not sure if it does for that device, as I've never tried it.
