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Altera_Forum's avatar
Altera_Forum
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10 years ago

Time Delay generation in EPM1270T144C5N CPLD

I have a signal, that is input to EPM1270T144CN. That is not a periodic signal. There are only two pulses. I want to delay them by 25 nsec at the output. Is there a way to do this, as per required ti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Raw delay but just going through signals is really hard to do and has really poor accuracy over PVT. My rough rule of thumb is that something can vary by 50%, i.e. if you delayed it by 33.33ns at the slow corner, it could be as fast as 16.66ns in the fast corner, so +/-8.33ns from your requirement. (I don't know why I'm using decimal points, as that's a really rough rule of thumb).

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Hi Rysc

If you do not mind, can you explain me how to do it ? I am very new to CPLD and FPGAs.