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Thanks for your response.
In this case. I create some filters by IP then put them into top module. It's cleare that I have to constraint paths between filters and IOs. But if the filter is quite big, time delay between them is significant, there some registers inside it (which I don't really know its structure) and there's risk that some paths inside it do not meet time requirement, so how does the tool does in this case? Is that true that the time requirement inside filter always meet and it work correctly? (if I constraint all path between filters and IOs)
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Once the tool knows the io timing and system clock(s) it will then check the entire register to register paths inside fpga from input register through all your filters and right to output register.
If you don't add io timing it will still check all paths except input registers and output registers because naturally it does not know what is coming in or going out to and will tell you so. If you have asynchronous reset again it can't check removal/recovery time unless that reset is registered first and will tell you so.
So if you pass timing then it means all internal paths are checked to be short enough for logic changes to be ready in one clock period.
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