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In principle you need to define various input clocks used in the fpga and io timing.
Additionally you may take risk and add internal deconstraints e.g. multicycle or false path if you know them. Otherwise a lower module need not any specific constraints. some ip vendors may have their own such deconstraints in which case you add them with a new path. Don't worry about lower modules, the whole project is viewed as one module by the tool and it needs to know system clock(s), io timing and then it checks all internal paths.
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Thanks for your response.
In this case. I create some filters by IP then put them into top module. It's cleare that I have to constraint paths between filters and IOs. But if the filter is quite big, time delay between them is significant, there some registers inside it (which I don't really know its structure) and there's risk that some paths inside it do not meet time requirement, so how does the tool does in this case? Is that true that the time requirement inside filter always meet and it work correctly? (if I constraint all path between filters and IOs)
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