--- Quote Start ---
Hello, There're some things I'm confusing about time constraint or my design.
Is there any time constraint, which is embedded to code of the IP core to constraint logics inside it?
Because some IP cores are very complicate to understand (for me). Do I need to take care it?
Similar, Can I embed time constraint file to every single component of a top level? If that, the design looks more simple, 'cause I just have to take care only components of the top, not every components of the sub-block.
--- Quote End ---
In principle you need to define various input clocks used in the fpga and io timing.
Additionally you may take risk and add internal deconstraints e.g. multicycle or false path if you know them. Otherwise a lower module need not any specific constraints. some ip vendors may have their own such deconstraints in which case you add them with a new path. Don't worry about lower modules, the whole project is viewed as one module by the tool and it needs to know system clock(s), io timing and then it checks all internal paths.
Honored Contributor
