the waitrequest of avalon

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These input and output registers can be there in either a 'fast' or 'slow' device. They are totally irrelevant to wait request, they do not alter the fundamental definition of when wait request should be asserted as mentioned above.

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My recommendation is to always add input and output registers to the Avalon bus, irrespective of whether I considered the device fast or slow. These registers then affect how you implement waitrequest, given that you then have to deal with the pipeline latency of the input read and write signals being delayed one clock before any control FSM can view them, and then the waitrequest signal being delayed by one more clock before it appears back on the Avalon bus, i.e., there can be two complete periods when the read/write signals can be asserted. If waitrequest is deasserted, then those two transactions would be accepted into the pipeline versus waitrequest being asserted, and no transactions being accepted.

Clearly you understand how to implement Avalon components. The original poster was asking for advice regarding whether or not to implement a combinatorial interface as shown in the Avalon specification.

If you like, we can both come up with some example slave interfaces, and timequest analysis to show why registers and FIFOs improve timing, and then post them to the Altera wiki.

Cheers,

Dave