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There's really only two hardware interfaces for custom slaves (ignoring Altera provided IP for DDR controllers and the like);
1) The slave is slow.
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2) The slave is fast.
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Your classifications of interfaces is incorrect and not necessary. An Avalon component needs to have a wait request or it must accept commands on every clock cycle. This is spelled out in the Avalon spec and has nothing to do with a slave that is 'fast' or 'slow'.
As an example where your classification breaks down, consider a simple fifo inside the slave. The fifo exists because the output at certain times cannot keep up with the input. The input side can accept new data on every clock cycle (so it would be 'fast' by your classification), but could fill up so it would need to have a wait request output which is connected to the fifo full signal. Having the wait request would make it 'slow' by your classification. So this example would be both 'fast' and 'slow' according to you. Your classification of 'fast' and 'slow' is meaningless and does nothing to define how to implement wait request.
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The examples shown in the Avalon-MM spec would require combinatorial paths to implement. They are not very good examples.
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Not true.
Kevin Jennings
Honored Contributor
