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Hi:
the output shoud use the register many paper write that,but I find that if the waitrequest output with register will lead to delay a
cycle.it is difficult to design the register timing.if use the combinational logic will solve the problem.but I am not sure whether it is reliable.
thank you!
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There's really only two hardware interfaces for custom slaves (ignoring Altera provided IP for DDR controllers and the like);
1) The slave is slow.
In this case, leave waitrequest asserted until the transaction occurs (read or write detected as asserted). This allows you to use both input and output registers on all signals. The latency does not really matter, since the device was slow anyway.
2) The slave is fast.
Eg., a block of on-chip registers or RAM.
For this case you simply leave waitrequest deasserted. There's really no problem accepting a write or read transaction on every clock and pipelining the transaction. Write address, byte-enables, and data get routed through pipeline registers into the RAM or control registers blocks. Read data is then delivered a few pipeline cycles later with the assertion of readdatavalid. Multiple back-to-back data phases are no problem.
These are the two approaches that give you the best timing results; given that both methods can use input and output registers.
The examples shown in the Avalon-MM spec would require combinatorial paths to implement. They are not very good examples.
TimeQuest timing analysis can be used to analyze the timing of your component designs.
Cheers,
Dave
Honored Contributor
