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Altera_Forum
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16 years ago

The voltage of I/O port from which a high frequency signal output

Hi, everyone! I'm a beginner in the Altera FPGA. Recently, I tried to use the output port of Cyclone 2C5 as the input clock of ADS830E (60MHz ADC). But I found when the output clock of FPGA ...
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Altera_Forum
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16 years ago

Have you selected the 3.3 V LVTTL I/O standard at pin assignments for all of your pins? This can be done easily with pin planner.

It is the ADC VDRV pin connected to the 3.3 v source?