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Altera_Forum
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14 years ago

The .vho generated is wrong?

Hi

I have a problem with the .vho file generated by Quartus.

When I make a complete compilation in Quartus, everything goes well. The functional simulation in Modelsim is good, timings too. But when I want to do the back-annotation simulation with the .vho generated, I get errors in Modelsim.

Here the error: 

#  vsim -do {do analyser_wave.do; run -all} -i –sdftyp /DUT=/Switch/timing/custom/switch_vhd.sdo -t ns -novopt work.switch_top 
   
 #  Loading std.standard
 #  Loading ieee.std_logic_1164(body)
 #  Loading std.textio(body)
 #  Loading ieee.vital_timing(body)
 #  Loading ieee.vital_primitives(body)
 #  Loading altera.dffeas_pack
 #  Loading altera.altera_primitives_components
 #  Loading stratixiv.stratixiv_atom_pack(body)
 #  Loading stratixiv.stratixiv_components
 #  Refreshing /Switch/simu_post_routage/work.switch_top(structure)
 #  Loading work.switch_top(structure)
 #  ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
 #     Time: 0 ns  Iteration: 0  Region: /
 #  SDF 6.6c Compiler 2010.08 Aug 23 2010
 #  Loading stratixiv.stratixiv_pllpack(body)
 #  Loading ieee.std_logic_arith(body)
 #  Loading ieee.std_logic_unsigned(body)
 #  Loading stratixiv.stratixiv_pll(vital_pll)
 #  Loading stratixiv.stratixiv_mn_cntr(behave)
 #  Loading stratixiv.stratixiv_scale_cntr(behave)
 #  Loading stratixiv.stratixiv_lcell_comb(vital_lcell_comb)
 #  Loading altera.dffeas(vital_dffeas)
 #  Loading stratixiv.stratixiv_ram_block(block_arch)
   
 #  ** Fatal: (vsim-3348) Port size (4) does not match actual size (144) for port '/switch_top/\DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32\/portadatain'.
 #     Time: 0 ns  Iteration: 0  Instance: /switch_top/\DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32\ File: /home/soft/Altera/10.1/Linux/RHEL4_2.6/quartus/eda/sim_lib/stratixiv_atoms.vhd Line: 3033
  
   
 #  FATAL ERROR while loading design
I don’t understand because it seems that the .vho generated is wrong..? What do you think? An idea of what I can do?

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi

    I looked in the .vho and I don’t understand.

    It creates a signal of 144 bits: 

    SIGNAL \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32_PORTADATAIN_bus\ : std_logic_vector(143 DOWNTO 0);
    It initializes it with 140 gnd and 4 useful bits: 

    \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
  & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & 
  gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
  & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & 
  gnd & gnd & gnd & gnd & gnd & \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|data_din~0_combout\ & 
  \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|data_din~1_combout\ & 
  \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|data_din~2_combout\ & 
  \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|sop_tmp~q\);
    But when it instantiates the component, it gives it just a bus of 4 bits: 

    -- Location: M9K_X62_Y21_N0
  \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32\ : stratixiv_ram_block
  -- pragma translate_off
  GENERIC MAP (
                  clk0_core_clock_enable => "ena0",
                  clk0_input_clock_enable => "ena2",
                  clk1_core_clock_enable => "ena3",
                  clk1_input_clock_enable => "ena3",
                  clock_duty_cycle_dependence => "on",
                  data_interleave_offset_in_bits => 1,
                  data_interleave_width_in_bits => 1,
                  logical_ram_name => "switch:DUT|MAC_System_0:the_MAC_System_0|MAC_System:mac_system_0|triple_speed_ethernet_0:the_triple_speed_ethernet_0|altera_tse_mac:altera_tse_mac_inst|altera_tse_top_gen_host:top_gen_host_inst|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g1k1:auto_generated|ALTSYNCRAM",
                  mixed_port_feed_through_mode => "dont_care",
                  operation_mode => "dual_port",
                  port_a_address_clear => "none",
                  port_a_address_width => 11,
                  port_a_byte_enable_clock => "none",
                  port_a_data_out_clear => "none",
                  port_a_data_out_clock => "none",
                  port_a_data_width => 4,
                  port_a_first_address => 0,
                  port_a_first_bit_number => 32,
                  port_a_last_address => 2047,
                  port_a_logical_ram_depth => 2048,
                  port_a_logical_ram_width => 36,
                  port_a_read_during_write_mode => "new_data_no_nbe_read",
                  port_b_address_clear => "none",
                  port_b_address_clock => "clock1",
                  port_b_address_width => 11,
                  port_b_data_out_clear => "none",
                  port_b_data_out_clock => "none",
                  port_b_data_width => 4,
                  port_b_first_address => 0,
                  port_b_first_bit_number => 32,
                  port_b_last_address => 2047,
                  port_b_logical_ram_depth => 2048,
                  port_b_logical_ram_width => 36,
                  port_b_read_during_write_mode => "new_data_no_nbe_read",
                  port_b_read_enable_clock => "clock1",
                  ram_block_type => "M9K")
  -- pragma translate_on
  PORT MAP (
                  portawe => \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|comb~0_combout\,
                  portbre => VCC,
                  clk0 => \DUT_PLL|altpll_component|auto_generated|wire_pll1_clk~clkctrl_outclk\,
                  clk1 => \DUT_PLL|altpll_component|auto_generated|wire_pll1_clk~clkctrl_outclk\,
                  ena0 => \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|comb~0_combout\,
                  ena2 => VCC,
                  ena3 => VCC,
                  portadatain => \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32_PORTADATAIN_bus\,
                  portaaddr => \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32_PORTAADDR_bus\,
                  portbaddr => \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32_PORTBADDR_bus\,
                  devclrn => ww_devclrn,
                  devpor => ww_devpor,
                  portbdataout => \DUT|the_MAC_System_0|mac_system_0|the_triple_speed_ethernet_0|altera_tse_mac_inst|top_gen_host_inst|U_MAC_TOP|U_MAC|U_TXFF|TX_DATA|U_RAM|altsyncram_component|auto_generated|ram_block1a32_PORTBDATAOUT_bus\);
    Any idea what is wrong?

    Thank you