the synthesis of a verilog program

hello all

i'm trying to convert my verilog program into a design just to see the circuit how they look like, the whole compilation was successful including synthesis but i couldn't find the corresponding designed file with the gates and registers,any ideas where should i look or where should i start? i had one design before (not in verilog) and i removed it from project but when i do the technology map viewer to see the circuits i still have it ..i didn't understand why it stays there...!!

cheers